1. Field of the Invention
The present invention generally relates to a code error detection system and, more particularly, to a code error detection apparatus for detecting bit errors in transmission codes in various types of digital transmission systems and apparatuses by using codes based on M-sequence (Maximal-length sequence) PRBS (Pseudorandom Bit Sequence) signals.
In addition, the present invention relates to a code error detection apparatus for detecting bit errors in transmission codes in various types of digital transmission systems and apparatuses by using codes based on M-sequence (Maximal-length sequence) PRBS (Pseudorandom Bit Sequence) signals and, more particularly, to an error detection apparatus for detecting bit errors in reception codes incorporated in burst frames.
2. Description of the Related Art
As is known, an ISDN (Integration Service Digital Network) is considered to be promising as a network which is capable of providing communication services associated with information of all kinds of media by means of a digital network.
The latest trend in information communication systems is to cope with a variety of high-speed multimedia. In order to meet such a need, a shift from a conventional narrow-band ISDN (N-ISDN) to a broad-band ISDN (B-ISDN) must be made.
The CCITT (International Telegraph and Telephone Consultative Committee) officially recommended (recommendation number I. 121) in November of 1990 to employ the ATM (Asynchronous Transfer Mode), which had been considered as a promising technique, so as to realize the above-mentioned B-ISDN. The ATM is a technique of performing high-speed multiplex conversion of information in units of fixed-length short cells by dividing the information into components and adding headers to the respective cells.
In mobile communication service systems, especially automobile telephone systems, a shift from a conventional analog scheme to a new digital scheme has been promoted to provide better services.
In digital information communication (i.e., code communication) systems including the above-described ATM transmission schemes and mobile communication schemes, the measurement evaluation of the overall system becomes increasingly important as the network is complicated owing to the diversification of services. In the case of the above-described code communication system, the signal transmission scheme is being shifted from consecutive code transmission to burst code transmission in which idle time intervals alternate with code transmission time intervals. Therefore, a measurement device for performing measurement evaluation of the system is required to cope with the shift.
It is known that detection of bit errors in codes transmitted from a transmitting section (test pattern generator) to a receiving section (error detector) forms the basis of measurement evaluation of such a code communication system (e.g., Hewlett-Packard Journal, March 1976, pp. 18 to 24 (see FIG. 8, especially)).
In addition, it is described in CCITT Recommendation 0.150-0.153 and the like that several types of maximal-length sequence (so called M-sequence) pseudorandom (PRBS) signals are used as test patterns used for such an error detector.
In RCR STD-27A for digital cellular telecommunication systems defined by the Research & Development Center for Radio Systems in Japan, it is also described that M-sequence PRBS signals (code length: 511 bits) conforming to CCITT V. 52 are used as test patterns.
In consideration of the above-described technical background, conventional code error detectors and their problems will be described below.
For example, when bit errors are to be detected in a code generated by a digital transmission system, a test signal generator 2 is connected to the signal input terminal of a target system 1 (to be tested), as shown in FIG. 49. A code based on an M-sequence PRBS signal as a test signal is transmitted from the test signal generator 2 to the target system 1, and bit errors in the transmission code are detected by a code error detection apparatus 3 connected to the signal output terminal of the target system 1.
As shown in FIG. 50, the test signal generator 2 incorporates an FSR (Feedback Shift Register) 6 comprising a shift register 4 consisting of series-connected m shift registers 4a and one or a plurality of EXOR gates (Exclusive OR circuits) 4b for calculating the exclusive OR of outputs from the registers 4a comprising the shift register 4. In addition, a switching circuit 8 connected to the input terminal of the first register 4a is connected to the EXOR gate 4b side so that a code based on a PRBS signal having a period of (2.sup.m -1) bits is generated by the FSR 6. For example, an FSR comprising by five registers has the arrangement shown in FIG. 51.
The code error detection apparatus 3 incorporates an FSR having the same arrangement as that of the FSR 6 of the test signal generator 2, and a comparator (not shown). This FSR generates a code (reference code) based on a PRBS signal of the same sequence as that of the test signal. Thereafter, the reception code from the target system 1 is compared with the code based on the PRBS signal as a reference to detect bit errors in the reception code which occur while passing through the target system 1.
Note that a state in which the FSR in the code error detection apparatus 3 is generating a reference code based on a PRBS signal of the same sequence as that of a test signal is regarded as a state in which the FSR is synchronous with a test signal. In an asynchronous state, if the reference code based on the PRBS signal generated by the FSR is compared with the reception code during an interval corresponding to at least m consecutive bits, non-coincidence is always detected in one of the bits. In other words, if the reference code based on the PRBS signal generated by the FSR is compared with the reception code during an interval corresponding to m consecutive bits, and no incoincidence is detected in any bit, it is determined that synchronization is established.
For example, the above-described code error detection apparatus has the arrangement shown in FIG. 52.
A reception code a based on an M-sequence PRBS signal and input through an input terminal 7 is supplied to the data terminal of a first register 4a in an FSR 9 identical to, e.g., the FSR shown in FIG. 50 which comprises by the series-connected m shift registers and the exclusive OR circuits, through one input terminal of a switching circuit 8 comprising two AND gates 8a and 8b, an OR gate 8c, and an inverter 8d. The reference code based on a PRBS signal b and output from the output terminal of the FSR 9 is input to one input terminal of an EXOR gate 10a comprising a comparator 10. At the same time, the reference code b based on the PRBS signal output from the FSR 9 is input to the other input terminal of the switching circuit 8. The switching circuit 8 is controlled by a switching signal c from a control section 11 comprising a central processing unit (CPU) and the like.
The reception code a input to the input terminal 7 is input to the switching circuit 8, and is simultaneously input to the other input terminal of the EXOR gate 10a. A clock signal corresponding to the bit rate of the reception code a, which is reproduced from the reception code a by a clock extracting circuit 12, is supplied to the clock terminal of the FSR 9. In addition, this reproduced clock signal is supplied to a counter 14 in the control section 11.
The comparator 10 compares each bit data of the reference code b based on the PRBS signal with corresponding bit data of the reception code a. Upon detection of incoincidence, the comparator 10 outputs an incoincidence detection signal d. The non-coincidence detection signal d output from the comparator 10 is input to the control section 11 and an error measurement section 13. For example, the error measurement section 13 counts input incoincidence signals to calculate an error rate.
An operation of the control section 11 in the code error detection apparatus 3 having such an arrangement will be described below with reference to the flow chart shown in FIG. 53.
The control section 11 sets the switching circuit 8 to the input terminal 7 side first by outputting the switching signal c of high (H) level (step P1). The control section 11 then sets a count value CN of the counter 14 to "0", and waits until the count value CN becomes m (step P2a). When the count value CN becomes m, the control section 11 determines that the m-bit data of the reception code a is set in the series-connected m shift registers comprising the FSR 9 (step p2b). When it is determined that the m-bit data is set in the FSR 9, the control section 11 changes the switching signal c to low (L) level to switch the switching circuit 8 to the output terminal side of the FSR 9 (step P3). As a result, the FSR 9 is set in a closed-loop state to be set in a self-running state so as to generate the reference code b based on the reference PRBS signal. At the same time, the control section 11 sets the count value CN of the counter 14 to "0" (step P4).
If it is determined in step P5 that the incoincidence detection signal d, i.e., an error detection signal, is input from the comparator 10, the flow returns to step P1. In step P1, the control section 11 switches the switching circuit 8 to the input terminal 7 side again to set the m-bit data of the reception code a in the FSR 9.
If no error detection signal is input in step P5, the control section 11 checks in step P6 whether the count value CN of the counter 14 has reached m. If NO in step P6, the flow returns to step P5 to check the presence/absence of an error detection signal again.
If it is determined in step P6 that the count value CN has reached m, it means that no incoincidence is detected after the reference code b based on the PRBS signal output from the FSR 9 is compared with the reception code a throughout m consecutive bits. At this time, therefore, the control section 11 determines that the synchronization of the reference code based on the PRBS signal output from the FSR 9 with respect to the reception code a is established.
When the synchronization is established, the control section 11 issues a command in step P7 to start bit error detection with respect to the reception code a. More specifically, in accordance with the error measurement command from the control section 11, the error measurement section 13 subsequently counts incoincidence detection signals d, i.e., error detection signals, output from the comparator 10 for a predetermined period of time, thus calculating a bit error rate.
A burst frame transmission scheme may be employed depending on the specifications and type of the target system 1 shown in FIG. 49. In this scheme, for example, signal transmission only in a predetermined time interval T.sub.B, and cessation of transmission in a succeeding predetermined time interval T.sub.C are repeated, as shown in FIG. 54. In this case, therefore, in the idle time interval T.sub.C, reception of the reception code a is stopped in the code error detection apparatus 3. For this reason, when bit errors in a transmitted code in this burst frame transmission scheme are to be measured by using M-sequence PRBS signals, pattern synchronization must be reestablished for each burst frame.
As a time interval T.sub.A required to establish the synchronization between the reception code a and the reference code b based on the PRBS signal from the start of a burst frame, at least a 2m-bit time interval is required with respect to the above-described FSR 9 consisting of m registers, and the length of the time interval varies depending on the state of occurrence of error bits in a code.
In a conventional code error detection apparatus, assuming that the synchronization between a reception code and a reference code based on a PRBS signal is established by the time the last bit of a burst frame is received, bit errors contained in the reception code a in the interval T.sub.A between the start of the burst frame and the establishment of synchronization cannot be properly detected. Therefore, an actual error measurement time interval T.sub.M is shortened by this time interval T.sub.A. The interval T.sub.A required for establishing synchronization is not a negligible value as compared with the burst frame time interval T.sub.B (280 bits). For example, the bit error rate of a whole burst frame cannot be correctly measured, because bit errors occurring in the time interval T.sub.A after which synchronization is established cannot be detected.
In addition, even in a transmission/reception system designed to perform normal consecutive data transmission/reception without using any burst frame, the conventional code error detection apparatus cannot start bit error detection from bit data at the start of bit error measurement.